1. Field of the Invention
Generally, the present disclosure relates to sophisticated integrated circuits including advanced transistor elements that comprise high-k metal gate electrode structures formed in an early manufacturing stage.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires a large number of circuit elements to be formed on a given chip area according to a specified circuit layout, wherein field effect transistors represent one important type of circuit element that determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for many types of complex circuitry, including field effect transistors, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, as the speed of creating the channel, which depends on the conductivity of the gate electrode, and the channel resistivity substantially determine the transistor characteristics, the scaling of the channel length, and associated therewith the reduction of channel resistivity and reduction of gate resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
Presently, the vast majority of integrated circuits are fabricated on the basis of silicon due to the substantially unlimited availability thereof, the well-understood characteristics of silicon and related materials and processes and the experience gathered over the last 50 years. Therefore, silicon will likely remain the material of choice in the foreseeable future for circuit generations designed for mass production. One reason for the importance of silicon in fabricating semiconductor devices has been the superior characteristics of a silicon/silicon dioxide interface that allows reliable electrical insulation of different regions from each other. The silicon/silicon dioxide interface is stable at high temperatures and, thus, allows the performance of subsequent high temperature processes, as are required, for example, for anneal cycles to activate dopants and to cure crystal damage without sacrificing the electrical characteristics of the interface.
For the reasons pointed out above, in field effect transistors, silicon dioxide has been preferably used as a gate insulation layer that separates the gate electrode, frequently comprised of polysilicon, from the silicon channel region. In steadily improving device performance of field effect transistors, the length of the channel region has been continuously decreased to improve switching speed and drive current capability. Since the transistor performance is controlled by the voltage supplied to the gate electrode to invert the surface of the channel region to a sufficiently high charge density for providing the desired drive current for a given supply voltage, a certain degree of capacitive coupling, provided by the capacitor formed by the gate electrode, the channel region and the silicon dioxide disposed therebetween, has to be maintained. It turns out that decreasing the channel length requires an increased capacitive coupling to avoid the so-called short channel behavior during transistor operation. The short channel behavior may lead to an increased leakage current and to a pronounced dependence of the threshold voltage on the channel length. Aggressively scaled transistor devices with a relatively low supply voltage and thus reduced threshold voltage may suffer from an exponential increase of the leakage current due to the required enhanced capacitive coupling of the gate electrode to the channel region that has typically been accomplished by decreasing the thickness of the silicon dioxide layer. For example, a channel length of approximately 0.08 μm may require a gate dielectric made of silicon dioxide as thin as approximately 1.2 nm. Although, generally, usage of high speed transistor elements having an extremely short channel may be restricted to high speed signal paths, whereas transistor elements with a longer channel may be used for less critical signal paths, the relatively high leakage current caused by direct tunneling of charge carriers through an ultra-thin silicon dioxide gate insulation layer may reach values for an oxide thickness in the range of 1-2 nm that may no longer be compatible with requirements for many types of integrated circuits.
Therefore, replacing silicon dioxide, or at least a part thereof, as the material for gate insulation layers has been considered. Possible alternative dielectrics include materials that exhibit a significantly higher permittivity so that a physically greater thickness of a correspondingly formed gate insulation layer nevertheless provides a capacitive coupling that would be obtained by an extremely thin silicon dioxide layer. It has thus been suggested to replace silicon dioxide with high permittivity materials such as tantalum oxide, strontium titanium oxide, hafnium oxide, HfSiO, zirconium oxide and the like.
When advancing to sophisticated gate architectures based on high-k dielectrics, additionally, transistor performance may also be increased by providing an appropriate conductive material for the gate electrode to replace the usually used polysilicon material, since polysilicon may suffer from charge carrier depletion at the vicinity of the interface to the gate dielectric, thereby reducing the effective capacitance between the channel region and the gate electrode. Thus, a gate stack has been suggested in which a high-k dielectric material provides enhanced capacitance even at a less critical thickness compared to a silicon dioxide layer, while maintaining leakage currents at an acceptable level. On the other hand, a metal-containing non-polysilicon material, such as titanium nitride and the like, may be formed so as to directly connect to the high-k dielectric material, thereby substantially avoiding the presence of a depletion zone. Since the conventional mechanisms for adjusting the work function of the gate electrodes, and thus the threshold voltage of the transistors, by an appropriate doping of the polysilicon material are no longer available in high-k metal gate electrodes, an appropriate adjustment of the effective work function with respect to the conductivity type of the transistor under consideration has to be implemented in the process flow for forming the high-k metal gate electrode structures.
For example, appropriate metal-containing gate electrode materials such as titanium nitride and the like may frequently be used in combination with appropriate metal species, such as lanthanum, aluminum and the like, so as to adjust the work function to be appropriate for each type of transistor, i.e., N-channel transistors and P-channel transistors, which may require an additional band gap offset for the P-channel transistor. For this reason, it has been proposed to appropriately adjust the threshold voltage of transistor devices by providing a specifically designed semiconductor material at the interface between the high-k dielectric material and the channel region of the transistor device, in order to appropriately “adapt” the band gap of the specifically designed semiconductor material to the work function of the metal-containing gate electrode material, thereby obtaining the desired low threshold voltage of the transistor under consideration. Typically, a corresponding specifically designed semiconductor material, such as silicon/germanium and the like, may be provided by an epitaxial growth technique at an early manufacturing stage, which may also represent an additional complex process step, which, however, may avoid complex processes for adjusting the work function and thus the threshold voltages in a very advanced process stage, as is the case in so-called replacement gate approaches.
It turns out, however, that the manufacturing sequence for forming the threshold adjusting semiconductor alloy may have a significant influence on transistor characteristics caused by an asymmetry of the process history of active regions of P-channel transistors and N-channel transistors during the complex manufacturing sequence for patterning the gate electrode structures. As is well known, the patterning of sophisticated gate electrode structures having a gate length of 50 nm and less requires very sophisticated lithography and etch techniques in combination with sophisticated deposition processes for providing the materials of the gate electrode structure. During the lithography, the deposition and the subsequent patterning processes, the existing topography of the semiconductor device may have a significant influence and thus great efforts are made in order to provide a substantially planar surface in the active regions and the adjacent isolation regions, which are provided so as to laterally delineate the active regions. To this end, typically, the process sequence is designed such that, for any etch processes and cleaning processes which may have to be applied during and after the manufacturing processes for forming the shallow trench isolations, the material consumption in the active regions, and in particular in the shallow trench isolations, may result in substantially the same height level prior to performing the manufacturing sequence for fabricating the complex gate electrode structures. For this purpose, the various processes may be assessed in advance in terms of material consumption and the like, and, based on these results, appropriate process adaptations, for instance an initial extra height of the shallow trench isolation regions and the like, may be appropriately adjusted.
When forming high-k metal gate electrode structures in an early manufacturing stage, in addition to the sophisticated lithography and patterning processes, additional material layers may have to be provided with a thickness of several angstrom to several nanometers, which may also require a superior initial surface topography prior to a gate patterning process. Moreover, after completing the complex gate electrode structures, any sensitive materials of the complex gate stacks may have to be reliably encapsulated on the basis of a thin dielectric material, such as silicon nitride, wherein the efficiency of the confinement may also depend on any preceding patterning related non-uniformities.
Since the incorporation of a threshold adjusting semiconductor alloy in one of the active regions, for instance for the P-channel transistors, introduces a certain degree of asymmetry, an inferior surface topography may be created prior to the actual gate patterning process, as will be described in more detail with reference to FIGS. 1a-1i. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 comprising a substrate 101 above which is formed a silicon-based semiconductor material 102 having an appropriate thickness for forming therein and thereabove transistors. Furthermore, an isolation structure 102C in the form of a shallow trench isolation is formed in the semiconductor layer 102, thereby laterally delineating and thus defining size and position of active regions 102A, 102B. In this context, an active region is to be understood as a semiconductor material in which an appropriate dopant profile is formed or is to be generated in order to form PN junctions for one or more transistors. In the example shown in FIG. 1a, the active region 102A corresponds to a P-channel transistor, while the active region 102B represents an N-channel transistor. Hence, the active regions 102A, 102B comprise an appropriate basic dopant concentration in order to determine the conductivity type of a P-channel transistor and an N-channel transistor, respectively. It should be appreciated that the active regions 102A, 102B may comprise or may receive other material species, such as germanium, carbon and the like, in order to appropriately adjust the overall electronic characteristics. As discussed above, in the active region 102A, an appropriate valence band offset is to be adjusted with respect to a sophisticated gate electrode structure that is still to be formed. For this purpose, an appropriate semiconductor alloy will be provided in the active region 102A, as will be described later on in more detail.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following conventional process strategies. First, the isolation structure 102C is formed by well-established lithography, etch, deposition and planarization techniques in which a trench is formed in the semiconductor layer 102 that is subsequently filled with a silicon dioxide material, for instance based on high density plasma chemical vapor deposition (CVD) and the like. After removing any excess material, the further processing is typically continued by performing a plurality of implantation processes using an appropriate masking regime in order to introduce the required dopant species for generating the basic dopant concentration in the active regions 102A, 102B so as to correspond to the type of transistor to be formed therein and thereabove. As explained above, the processes for forming the isolation structure 102C, the removal of any mask materials and the subsequent process sequence for incorporating the well dopant species may be designed such that a substantially planar surface topography is obtained with respect to the active regions 102A, 102B and the isolation region 102C. After activating the dopant species in the active regions 102A, 102B and re-crystallizing implantation-induced damage, the further processing is continued by exposing the device 100 to an oxidizing ambient 110, which is typically established on the basis of elevated temperatures, for instance in the range of 700-1200° C., and supplying oxygen in order to obtain a desired oxidation rate of the exposed surface areas of the active regions 102A, 102B. Thus, during the oxidation process 110, a mask layer 104 is formed in a well-controllable manner having a thickness of, for instance, 10 nm or less.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which an etch mask 105, such as a resist mask, is formed above the semiconductor device 100 such that the mask material 104 on the first active region 102A is exposed, together with a portion of the isolation region 102C, while the mask material 104 formed on the second active region 102B and an adjacent portion of the isolation region 102C are protected by the mask 105. The etch mask 105 is formed by well-established lithography techniques. Thereafter, an etch process is applied in order to selectively remove the mask material 104 from the first active region 102A, which is accomplished by using diluted hydrofluoric acid (HF), which allows a selective removal of silicon dioxide material while substantially not attacking silicon material. Consequently, during the etch process based on HF, the exposed portion of the trench isolation region 102C also suffers from a material loss.
FIG. 1c schematically illustrates the semiconductor device 100 after the selective removal of the mask material 104 and the removal of the etch mask 105 (FIG. 1b). As illustrated, due to the preceding etch process, a certain material loss has been created in the isolation structure 102C adjacent to the active region 102A, while the previously covered portion may have the initial height.
FIG. 1d schematically illustrates the semiconductor device 100 when exposed to a further reactive process ambient 106, which includes a cleaning process and the like in order to prepare the device 100 for the subsequent deposition of a silicon/germanium alloy selectively on the first active region 102A. The process 106 is typically established on the basis of any appropriate chemistry in order to remove contaminants and the like which may have been created during the previous removal of the etch mask and the like. Typically, the cleaning process 106 causes a certain degree of material erosion of the mask 104, thereby reducing a thickness thereof, as indicated by 104R, however, without actually exposing surface portions of the second active region 102B. Similarly, a certain material loss may occur in the isolation structure 102C, however, in a substantially identical manner adjacent to the active region 102A and adjacent to the active region 102B.
FIG. 1e schematically illustrates the semiconductor device 100 during a selective epitaxial growth process 107 in which process parameters, such as temperature, pressure, flow rates of precursor gases and the like, are appropriately selected such that a material deposition is substantially restricted to exposed silicon surface areas, while the dielectric surfaces may substantially prevent a deposition of material. Hence, during the process 107, a silicon/germanium material 108 is selectively formed in the active region 102A, wherein the thickness and material composition of the layer 108 may provide the desired adaptation of the electronic characteristics in order to obtain the desired threshold voltage for the transistor still to be formed in and above the active region 102A.
FIG. 1f schematically illustrates the device 100 in a further advanced manufacturing stage in which a further etch process 109 is performed on the basis of hydrofluoric acid in order to remove the mask layer 104 from the active region 102B. As discussed above, hydrofluoric acid is a very selective etch chemistry with respect to silicon-based materials, thereby substantially not attacking the materials in the active regions 102A, 102B. On the other hand, a further material loss may occur in the isolation region 102C, thereby in particular increasing the height difference between the active region 102A and the adjacent portion of the isolation structure 102C. Consequently, the further processing is based on a significant topography, in particular in the vicinity of the active region 102A.
FIG. 1g schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a gate electrode structure 130A is formed on the active region 102A, i.e., on the threshold adjusting semiconductor layer 108, and a gate electrode structure 130B is formed on the active region 102B. The gate electrode structures 130A, 130B may basically have a similar configuration, for instance in view of critical dimension and material composition, except for any differences as required for adjusting a different work function and thus threshold voltage for transistors to be formed on the basis of the gate electrode structures 130A, 130B. For example, the gate electrode structure 130A may comprise a thin dielectric material 131, such as a silicon oxynitride material, in combination with a high-k dielectric material 132A and a metal-containing cap layer or electrode material 133A, such as titanium nitride and the like. Moreover, a further electrode material 134 in the form of a silicon material, a silicon/germanium material and the like is typically provided in combination with a dielectric cap layer 135, such as a silicon nitride material, a silicon dioxide material and the like. Similarly, the gate electrode structure 130B comprises the dielectric material 131 and a high-k dielectric material layer 132B in combination with a metal-containing electrode material 133B, followed by the semiconductor material 134 and the dielectric cap material 135. Depending on the process and device requirements, the high-k dielectric materials 132A, 132B and/or the metal-containing electrode materials 133A, 133B may differ, for instance with respect to the incorporation of the appropriate work function adjusting metal species, such as aluminum for P-channel transistors, lanthanum for N-channel transistors and the like.
As previously explained, generally, the patterning of gate electrode structures having a length of 50 nm and less requires sophisticated deposition processes, lithography and patterning strategies, which may be influenced by the local surface topography. In particular, the incorporation of additional material systems, such as the layer 132A, 133A and 132B, 133B, in addition to conventional material systems, such as the layers 131 and 134, may result in different layer thickness values above the active regions 102A, 102B due to the different local topography. Similarly, during the subsequent complex lithography and etch processes, a difference in local surface topography in combination with the previously induced non-uniformities may additionally contribute to a different process result, for instance in terms of a different critical dimension of the gate electrode structures 130A, 130B, the cross-sectional shape, in particular at the foot of the gate electrode structures 130A, 130B, and the like.
For example, the formation of the material 131 and subsequently the deposition of the high-k dielectric material for the layers 132A, 132B may require process strategies requiring a high degree of conformal deposition behavior in order to provide the desired final characteristics of a gate dielectric material composed of the layers 131 and 132A, 132B, respectively. Similarly, typically, work function adjusting species have to be provided on the basis of moderately thin metal layers, which may have to be patterned prior to the actual patterning of the gate electrode structures 130A, 130B, wherein the local different surface topography may also result in non-desired irregularities. Similarly, the deposition of the materials 133A, 133B may also be influenced by the surface topography. It should be appreciated that typically a plurality of process strategies are available for appropriately adjusting the work function and thus threshold voltage in the gate electrode structures 130A, 130B, such as sophisticated diffusion processes and the like, wherein any variation in layer thickness, for instance caused by the pronounced surface topography, may result in a corresponding variation of transistor characteristics.
FIG. 1h schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which a liner material 136, such as a silicon nitride material, may be deposited with a thickness of several nanometers in order to confine sensitive material in the gate electrode structures 130A, 130B, such as the materials 132A, 133A, 132B, 133B. For example, a reliable coverage of sidewalls of these materials may also strongly depend on the previous process results upon patterning the gate electrode structures 130A, 130B so that the actual confinement by the layer 136 may also be different for the different gate electrode structures. Consequently, generally, an increased thickness of the layer 136 may have to be implemented in order to ensure a reliable confinement of each of the gate electrode structures 130A, 130B, which, however, on the other hand, may negatively influence the overall transistor characteristics.
FIG. 1i schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a P-channel transistor 150A is formed in and above the active region 102A and comprises the gate electrode structure 130A. Similarly, a transistor 150B, such as an N-channel transistor, is formed in and above the active region 102B and comprises the gate electrode structure 130B. The transistors 150A, 150B comprise drain and source regions 152, for instance in combination with metal silicide regions 153 provided therein. Furthermore, metal silicide regions 137 may also be formed in the gate electrode structures 130A, 130B. Additionally, a spacer structure 151 may be formed on sidewalls of the gate electrode structures 130A, 130B, for instance on the liner 136, that is typically preserved throughout the entire process flow for confining the sensitive materials in the gate electrode structures 130A, 130B, as discussed above.
The transistors 150A, 150B as illustrated in FIG. 1i may be formed on the basis of any appropriate process strategy, wherein, starting from the configuration as shown in FIG. 1h, the liner 136 may be formed into spacer elements by any appropriate etch process, possibly in combination with the provision of any additional sidewall spacer elements, which may be accomplished by well-established etch strategies. If required, a strain-inducing semiconductor material may be provided in the active region 102A, for instance in the form of a silicon/germanium material and the like. Similarly, a silicon/carbon material may be incorporated in the active region 102B if a corresponding strain-inducing mechanism is required for the transistor 150B. Thereafter, the spacer structure 151 in combination with the drain and source regions 152 are provided on the basis of well-established masking regimes and implantation techniques, followed by anneal processes. Thereafter, the metal silicide regions 153 and 137 may be formed, wherein, at any appropriate manufacturing stage, the dielectric cap materials 135 (FIG. 1g) may have been removed in order to expose the semiconductor material 134 of the gate electrode structures 130A, 130B. Thereafter, the further processing may be continued by forming an interlayer dielectric material and providing contact elements therein so as to connect to the transistors 150A, 150B.
Thus, the above-described process strategy may represent a very promising approach for providing sophisticated transistors on the basis of high-k metal gate electrode structures, wherein, however, undue fluctuations in transistor characteristics may be observed, which may be strongly correlated to the pronounced surface topography in the isolation regions.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.